Event: International Wafer-Level Packaging Conference - IWLPC, Santa Clara, Nov 4-5, 2011
Peter Ramm, Fraunhofer EMFT actively controbuted to the IWLPC Panel Discussion and discussed:
- 3D-IC integration (TSV-Technology for 3D-integrated ICs) is seen as (too) expensive and because of that delayed to 2015 or later
- So-called 2.5D integration (Si Interposers) with cost issues too (relatively expensive in comparison to performance achieved) - alternative glass interposer concept presented by Rao Tumalla / GiorgiaTech
- 3D memory stacks (TSV in periphery) will come soon (2012)
- Heterogeneous MEMS/IC integration is recognized as one of the key drivers for 3D TSV integration (e-BRAINS !) because TSVs just on densities of global interdconnect level - instead of very high densities for 3D-ICs. Focus on Reliability not on integration density !