3D Integration

Lead partners: Fraunhofer, IMEC, Infineon, Sensonor, Siemens, SINTEF, Tyndall, 3D-PLUS

Research and technological development to achieve highly-reliable and robust processes for stacking and vertical interconnection of fully processed devices by wafer-level 3D integration of known good dies (KGD).

  • Low Temperature TSV Technology for Reliable Heterogeneous Systems; Lead partners: Tyndall, Fraunhofer EMFT
  • High Performance Interposer Technology
    Lead partners: Siemens, Fraunhofer EMFT
  • Robust Handling Concept for Heterogeneous Integration of KGDs
    Lead partner: Fraunhofer EMFT
  • Layer Transfer Wafer Bonding
    Lead partners: SINTEF, Sensonor
  • 3D-System In Package (3D-SIP) for Ultra-Miniaturized Heterogeneous Systems;
    Lead partner: 3D-PLUS
  • 3D-Wafer Level Packaging (3D-WLP);
    Lead partners: IMEC, Fraunhofer EMFT, Infineon

TSV-technologies with low-temperature bonding for highly reliable 3D-integrated heterogeneous systems (stacks with ICs and MEMS/NEMS) will be developed on the base of two bonding schemes:

  • TSV-SWACF technology with sub-micron-anisotropic conductive film bonding
  • TSV-SLID technology with low-temperature Solid-Liquid-Interdiffusion bonding

Multichip wiring technology by Siemens for high performance interposer technology includes photo assisted electrochemical etch to generate high aspect ratio vias in silicon. It will allow extreme fine interposer TSV 10µm… 1µm at independent silicon thickness of 50µm…900µm. Metallization of TSVs by liquid conductor fill.

Layer transfer wafer bonding is dedicated to the heterogeneous integration of quantum wells (QWs) and electronic read-out circuitry. The technology will be optimized in order to fulfill several requirements especially with regard to bond strength, wafer alignment and reliability.

3D-SIP technology will be optimized based on the patented TPV (Through Polymer Via) technology of 3D-PLUS in order to demonstrate the technology on Known Good Wafer with pitches down to 50 µm.

3D-WLP development of thin die embedding processes based on Ultra Thin Chip Stacking (UTCS) process. Screening of new polymers will be done with respect to reliability.

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